The present disclosure relates to layouts of logic cells used for logic LSI circuits, and particularly to layouts of logic cells including MIS transistors, each of which has a source/drain made of Si mixed crystal.
In order to improve performance of CMOS devices, strained Si technology has been introduced, in which tensile/compressive strain is applied to a gate-channel portion to improve mobility of electrons or holes. As known strained Si technology, for example, a contact liner film is formed on a MIS transistor, and tensile strain is applied to a channel from a side surface of a gate electrode to improve the drive capability of the MIS transistor. However, in the technology using a contact liner film, a gate pitch decreases with advancing generations to prevent an increase in thickness of the contact liner film. It is considered that this may lead to difficulty in applying sufficient strain to a channel from a side surface of a gate. Therefore, new technology for improving the drive capability of a MIS transistor is required.
As a type of new technology, more strain is applied to a channel by using a Si mixed crystal layer buried in a substrate as a source/drain region of a MIS transistor. This technology is expected to be promising. In the technology, a silicon germanium (SiGe) layer is used for a source/drain region of a P-channel type MIS transistor (hereinafter referred to as a “P-type MIS transistor”), and a silicon carbide (SiC) layer is used for a source/drain region of an N-channel type MIS transistor (hereinafter referred to as an “N-type MIS transistor”) so as to apply strain to a channel, which is a part of a silicon substrate. This technology is described in, for example, IEDM (International Electron Device Meeting) Technical Digest, pp. 1070-1072, 2005.
The following is description of an example of applying to a logic LSI, technology using a Si mixed crystal layer for a source/drain region of a MIS transistor. A logic LSI is conventionally designed by combining hundreds of logic cells, each of which includes a plurality of MIS transistors.
FIGS. 5A and 5B illustrate example circuit structures of a 2 input NAND gate and a 2 input NOR gate, respectively. FIG. 6 is a layout diagram, in which a 2 input NAND gate (on the left side) and a 2 input NOR gate (on the right side) are adjacent to each other in a gate length direction of MIS transistors (i.e., the horizontal direction in the drawing) in a conventional semiconductor device.
FIGS. 7A and 7B are cross-sectional views of the conventional semiconductor device taken along lines VIIa-VIIa, and VIIb-VIIb in FIG. 6.
In this example, as shown in FIG. 6 as well as FIGS. 7A and 7B, an N-type well region 103a, and a P-type well region 103b adjacent to the N-type well region 103a in a gate width direction (i.e., the vertical direction in FIG. 6) are formed on a semiconductor substrate 101 made of silicon. The N-type well region 103a includes an N-type substrate contact region 121e. The N-type substrate contact region 121e is arranged adjacent to active regions 121a and 121b in the gate width direction when viewed from the active regions 121a and 121b, and is coupled to a power source line (or a power source terminal) VDD through a substrate contact. The P-type well region 103b includes a P-type substrate contact region 121f. The P-type substrate contact region 121f is arranged adjacent to active regions 121c and 121d in the gate width direction when viewed from the active regions 121c and 121d, and is coupled to a ground line (or a ground terminal) VSS through a substrate contact. The active regions 121a, 121b, 121c and 121d, the N-type substrate contact region 121e, and the P-type substrate contact region 121f are surrounded by an isolation region 102 having a shallow trench isolation (STI) structure.
P-type MIS transistors MP1 and MP2 constituting the NAND gate are formed in the active region 121a, and P-type MIS transistors MP3 and MP4 constituting the NOR gate are formed in the active region 121b. 
N-type MIS transistors MN1 and MN2 constituting the NAND gate are formed in the active region 121c, and N-type MIS transistors MN3 and MN4 constituting the NOR gate are formed in the active region 121d. 
Furthermore, a gate line 5G1 including gate electrodes of the P-type MIS transistor MP1 and the N-type MIS transistor MN1, and a gate line 5G2 including gate electrodes of the P-type MIS transistor MP2 and the N-type MIS transistor MN2 are formed to extend from a top of the active region 121a to a top of the active region 121c with a gate insulating film 104 interposed between the gate lines and the active regions. A gate line 5G3 including gate electrodes of the P-type MIS transistor MP3 and the N-type MIS transistor MN3, and a gate line 5G4 including gate electrodes of the P-type MIS transistor MP4 and the N-type MIS transistor MN4 are formed to extend from a top of the active region 121b to a top of the active region 121d with the gate insulating film 104 interposed between the gate lines and the active regions.
As shown in FIG. 7A, each of the P-type MIS transistors MP1, MP2, MP3, and MP4 includes, other than the gate insulating film 104 and the gate electrode; P-type extension regions 106a, P-type source/drain regions 108a, sidewall spacers 107, a silicide layer 109 on the source/drain regions, and a silicide layer 130 on the gate. As shown in FIG. 7B, each of the N-type MIS transistors MN1, MN2, MN3, and MN4 includes, other than the gate insulating film 104 and the gate electrode; N-type extension regions 106b, N-type source/drain regions 108b, sidewall spacers 107, the silicide layer 109 on the source/drain regions, and the silicide layer 130 on the gate. Furthermore, the semiconductor device includes an interlayer insulating film 110 for burying the MIS transistors, contact plugs 111 penetrating the interlayer insulating film 110, and metal wires 112 coupled to the contact plugs 111. Note that, reference characters A1 and B1 in FIG. 6 denote input terminals of the NAND gate, and Y1 denotes an output terminal of the NAND gate. On the other hand, A2 and B2 denote input terminals of the NOR gate, Y2 denotes an output terminal of the NOR gate.
In the conventional semiconductor device, the P-type source/drain regions 108a of the P-type MIS transistors MP1, MP2, MP3, and MP4 are formed of SiGe layers buried in recesses provided in the active regions 121a and 121b. The SiGe layers apply compressive stress to channel regions of the P-type MIS transistors made of silicon to improve mobility of carriers.
Furthermore, the P-type MIS transistors MP1 and MP4, which are adjacent to each other, are electrically separated by an isolation region 102A. Each of the P-type MIS transistors MP2 and MP3 is electrically separated from a P-type MIS transistor (not shown) by the isolation region 102.
When forming the P-type source/drain regions 108a, the isolation regions 102 and 102A, the gate lines 105G1, 105G2, 105G3, and 105G4, the P-type extension regions 106a, and the sidewall spacers 107 are formed at first. Then, the active regions 121a and 121b are etched to form recesses in side regions of the gate lines 105G1, 105G2, 105G3, and 105G4. Then, the SiGe layers containing P-type impurities are selectively epitaxially grown within the recesses to form the P-type source/drain regions 108a. 